This invention relates to the fabrication and structure of field-effect transistors (xe2x80x9cFETsxe2x80x9d) of the insulated-gate type. All of the insulated-gate FETs (xe2x80x9cIGFETsxe2x80x9d) described below are enhancement-mode devices except as otherwise indicated.
An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone that extends between a source and a drain. The channel zone in an enhancement-mode IGFET is part of a body region that forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all semiconductor body material between the source and drain.
FIG. 1 illustrates a conventional symmetrical n-channel enhancement-mode IGFET 10 provided with a two-part drain for reducing undesired hot-carrier injection. IGFET 10 is created from a monocrystalline silicon semiconductor body having region 12 of lightly doped p-type body material. IGFET 10 has n-type source 14, n-type drain 16, intervening p-type channel zone 18, gate electrode 20, gate dielectric layer 22, and gate sidewall spacers 24 and 26. Drain 16 consists of heavily doped main portion 16M and more lightly doped extension 16E. Source 14 similarly consists of heavily doped main portion 14M and more lightly doped extension 14E. When IGFET 10 is turned on, electrons travel from source 14 to drain 16 by way of a thin channel induced in channel zone 18 along the upper semiconductor surface.
A pair of depletion regions extend respectively along the drain/body and source/body junctions. Under certain conditions, especially when the channel length is small, the drain depletion region can extend laterally to, and merge with, the source depletion region. This phenomenon is termed punchthrough. If the drain depletion region punches through to the source depletion region, the operation of IGFET 10 cannot be controlled with gate electrode 20. Accordingly, punchthrough normally needs to be avoided.
One conventional technique for inhibiting punchthrough in an IGFET as channel length is reduced, and also for alleviating roll-off of the threshold voltage at short channel length, is to increase the net dopant concentration of the channel zone in a pocket along the source. See Ogura et al, xe2x80x9cA Half Micron MOSFET Using Double Implanted LDD,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, Dec. 11-15, 1982, pages 718-721. As an artifact of creating the increased-concentration pocket along the source, the dopant concentration in the channel zone is commonly increased in a corresponding pocket along the drain. Per Codella et al, xe2x80x9cHalo Doping Effects in Submicron DI-LDD Device Design,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, Dec. 1-4, 1985, pages 230-233, the pockets are commonly referred to as xe2x80x9chaloxe2x80x9d.
FIG. 2 depicts a conventional symmetrical n-channel enhancement-mode halo IGFET 30 as configured in Ogura et al or Codella et al. Except as described below, IGFET 30 contains the same regions as IGFET 10 in FIG. 1. As shown in FIG. 2, channel zone 18 in n-channel IGFET 30 includes a pair of p-type halo pockets 31 and 32 doped more heavily than the remainder of channel zone 18. Halo pockets 31 and 32 are situated along the inner boundaries of source 14 and drain 16 so as to inhibit punchthrough. Metal silicide layers 33, 34, and 35 respectively contact components 14M, 16M, and 20. Portion 36 of channel zone 18 contains ion-implanted p-type threshold-adjust dopant.
Halo pockets 31 and 32 can be created in various ways. For example, p-type halo dopant is typically ion implanted through the upper semiconductor surface into the semiconductor body using gate electrode 20 as an implantation shield. The halo implant can be performed roughly perpendicular to the upper semiconductor surface as indicated in Ogura et al.
The halo implant can also be performed at a substantial angle to a perpendicular to the upper semiconductor surface. In this regard, see (a) Su, xe2x80x9cTilt Angle Effect on Optimizing HALO PMOS Performance,xe2x80x9d 1997 Int""l Conf. Simulation Semicon. Procs. and Devs., Sep. 8-10, 1997, pages 33-36, (b) Rodder et al, xe2x80x9cA Sub-0.18 xcexcm Gate Length CMOS Technology for High Performance (1.5 V) and Low Power (1.0 V),xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, Dec. 8-11, 1996, pages 563-566, and (c) Hori, xe2x80x9cA 0.1-xcexcm CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS),xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, Dec. 11-14, 1994, pages 75-78.
As indicated above, a halo pocket is needed only at the source to alleviate the short-channel effects of punchthrough and threshold voltage roll-off. In fact, having a halo pocket at the drain can increase the threshold voltage and lower the drive current. Consequently, the performance of symmetrical IGFET 30 can be less than what would occur if halo pocket 32 were not present along drain 16.
FIG. 3 depicts a conventional asymmetrical n-channel enhancement-mode halo IGFET 38 configured as described in Hwang, U.S. Pat. No. 5,364,807, so as to have a halo pocket only along the source. Except as described below, IGFET 38 contains the same regions as IGFET 10 in FIG. 1. As illustrated in FIG. 3, halo pocket 31 is situated along source 14 in IGFET 38. IGFET 38 does not have a halo pocket along drain 16. With gate dielectric layer 22 extending laterally beyond gate electrode 20, IGFET 38 has gate sidewall spacer 26 along the drain side of electrode 20 but lacks a sidewall spacer along the source side of electrode 20.
FIG. 4 illustrates how halo pocket 31 is formed along source 14 without forming a corresponding halo pocket along drain 16. A source-side gate sidewall spacer is utilized in creating source 14. After source 14 and drain 16 are formed, a photoresist mask 39 having a opening above the source-side spacer is provided along the upper surface of the structure. The source-side spacer is removed. P-type dopant is ion implanted vertically through the mask opening to define source-adjoining halo pocket 31. Mask 39 and drain-side spacer 26 prevent a corresponding halo pocket from being formed along drain 16.
While the asymmetrical structure of IGFET 38 can enhance device performance, the technique utilized to create source-adjoining halo pocket 31 without creating a drain-adjoining halo pocket requires an extra masking step. This is disadvantageous since masking operations tend to be relatively costly. The photolithographic layout of mask 39 has to be very accurate because the opening in mask 39 needs to overlie the source-side spacer. Also, it is typically desirable to provide metal silicide regions along components 14, 16, and 20 at a point near the end of the IGFET fabrication process. Since a source-side gate sidewall spacer is not present in the final structure of IGFET 38, attempting to provide such metal silicide regions can result in the metal silicide along gate electrode 20 bridging to the metal silicide along source 14. Consequently, electrode 20 can be electrically shorted to source 14, thereby making IGFET 38 useless as a switching device.
Other techniques have been investigated for creating asymmetrical IGFETs in which a halo pocket is present along the source but not along the drain. For example, see Buti et al, xe2x80x9cAsymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half Micron n-MOSFET Design for Reliability and Performance,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, Dec. 3-6, 1989, pages 617-620. In general, each of these other techniques requires an additional masking operation or/and incurs other disadvantages. It is desirable to create an asymmetrical IGFET so that its channel zone is doped more heavily along the source than along the drain without necessitating any additional masking operation and without causing performance degradation.
The present invention utilizes a combination of mask shadowing and angled ion implantation for doping a channel zone of an insulated-gate field-effect transistor more heavily along one of the IGFET""s two source/drain zones than along the other source/drain zone. Since one end of the channel zone is doped more heavily at one end than the other, the IGFET is an asymmetrical device. The source/drain zone that adjoins the more heavily doped end of the channel zone normally functions permanently as the source. The other source/drain zone then normally functions permanently as the drain.
More particularly, according to one aspect of the invention, a gate electrode for an IGFET is furnished generally above, and vertically separated by gate dielectric material from, an intended location for a channel zone in a semiconductor body. A mask, typically formed with actinic material, is provided over the semiconductor body and the gate electrode. The mask has a mask opening which at least partially overlies the gate electrode. The mask opening defines a pair of transverse mask sides (or edges) located laterally beyond the gate electrode and any material situated on the gate electrode""s two transverse sides.
Angled ion implantation, i.e., implantation in which ions impinge significantly non-perpendicularly on the structure being implanted, is now performed with semiconductor dopant through the mask opening to dope the channel-zone location more heavily along one end than along the other end. The asymmetrical doping characteristic is achieved by causing ions of a species of the dopant to pass in an angled manner through the opening and enter the semiconductor body close to the lower edge of largely only one of the transverse sides of the gate electrode. The ions then enter the channel-zone location and, because they pass close to the lower edge of largely only one of the gate electrode""s transverse sides, are more heavily concentrated at the end of the channel-zone location closest to that transverse side of the gate electrode than at the other end of the channel-zone location. When the primary dopant is of the same conductivity type as the channel-zone location, the end of the channel zone receiving the heavier ion concentration is more heavily doped.
Angled implantation in this aspect of the invention is performed from two significantly different angular orientations relative to the semiconductor body. Each angular orientation is characterized by an average tilt angle to the vertical and an average azimuthal angle as measured in a plane extending generally along the upper surface of the semiconductor body. While the tilt angles are normally close to each other, preferably the same, the azimuthal angles are very different, typically 180xc2x0 apart.
The location and shape (or size) of the mask opening are controlled during the mask-providing step so that the dopant species ions impinging from largely only one of the two angular orientations pass close to the indicated lower transverse edge of the gate electrode and enter the channel-zone location. The ions that impinge from the other angular orientation are substantially blocked by the mask, the gate electrode, and any material along the gate electrode from entering the channel-zone location. In particular, the ions impinging from this other orientation are shadowed (blocked) by the mask from passing close to the other lower transverse edge of the gate electrode. While these ions do not cause a significant doping change in the channel-zone location, they normally enter the semiconductor body elsewhere during the angled implantation and thus cause doping changes elsewhere in the semiconductor body.
The angled implantation at one of the angular orientations specifically entails directing first ions of the semiconductor species toward the mask at an average tilt angle of at least 15xc2x0, normally at least 25xc2x0, along paths that originate laterally beyond one of the mask""s transverse sides. The angled implantation at the other angular orientation then entails directing second ions of the dopant species toward the mask at a second average tilt angle of at least 15xc2x0, likewise preferably at least 25xc2x0, along paths that originate laterally beyond the mask""s other transverse side.
The mask opening utilized for asymmetrically doping the channel zone is preferably also employed for introducing further semiconductor dopant into the semiconductor body to at least partially form a pair of source/drain zones for the IGFET. Consequently, no additional masking operation is needed to asymmetrically dope the channel zone. There is no need to perform any operation which might damage the IGFET""s performance. For example, when a sidewall spacer is provided along the gate electrode in forming each source/drain zone as a main portion and a more lightly doped extension, neither of the sidewall spacers needs to be removed in order to asymmetrically dope the channel zone. The invention thus avoids the disadvantages of Hwang cited above.
At a given leakage current, an asymmetrical IGFET fabricated according to the invention has greater drive current than an otherwise comparable symmetrical halo-doped IGFET. That is, the ratio of drive current to leakage current is increased in the invention. This enables the present asymmetrical IGFET to switch faster between the on and off states than an otherwise comparable symmetrical halo-doped IGFET. Accordingly, the invention furnishes a highly economical technique for asymmetrically doping an IGFET""s channel zone to achieve high performance.
Mask shadowing and angled ion implantation are typically utilized in accordance with the invention to doped intended locations for the channel zones of two IGFETs so that one of the channel-zone locations is doped asymmetrically while the other is doped symmetrically or asymmetrically. Specifically, in a further aspect of the invention, primary and additional gate electrodes are respectively furnished over, and vertically separated by gate dielectric material from, laterally separated primary and additional channel-zone locations in a semiconductor body. A mask is provided over the semiconductor body and the gate electrodes. The mask has one or more mask openings which at least partially overlie the gate electrodes and which, for each gate electrode, define first and second mask sides located laterally beyond that gate electrode and any material situated on its two transverse sides.
First ions of a semiconductor dopant species are directed towards the mask at a first average tilt angle of at least 15xc2x0 along paths that originate laterally beyond the mask""s first transverse sides. The location and shape (or size) of the mask opening(s) is controlled so that an electrically significant amount of the first ions passes through one such mask opening and enters the primary channel-zone location while the combination of the mask, the additional gate electrode, and any material along the additional gate electrode substantially blocks any electrically significant amount of the first ions from entering the additional channel-zone location.
Second ions of the dopant species are directed toward the mask at a second average tilt angle of at least 15xc2x0 along paths that originate laterally beyond the mask""s second transverse sides. The location and shape of the mask opening(s) can be controlled in such a way that the mask, the primary gate electrode, and any material along the primary gate electrode substantially block any electrically significant amount of the second ions from entering the primary channel-zone location while allowing an electrically significant amount of the second ions to pass through one such mask opening and enter the additional channel-zone location. The end result is that both channel-zone locations are doped asymmetrically with the asymmetries arranged in an opposite orientation relative to each other.
Alternatively, the location and shape of the mask opening(s) can be controlled so that an electrically significant amount of the second ions passes through the mask opening(s) and enters both channel-zone locations. As a further alternative, the location and shape of the mask opening(s) can be controlled so that the mask, the gate electrodes, and any material along the gate electrodes substantially block any electrically significant amount of the second ions from entering either channel-zone location. By using either of these two alternatives, one of the channel zones is doped asymmetrically while the other channel zone is doped symmetrically.
The present invention furnishes a semiconductor structure containing two like-polarity IGFETs such as those produced by using the first-mentioned alternative in which the second ions enter both channel-zone locations. The two IGFETs are provided along an upper surface of a semiconductor body having body material. Each IGFET has a channel zone of the body material, a pair of source/drain zones separated by the channel zone, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer above the channel zone.
The channel zone of one of the IGFETs is doped more heavily along one of its source/drain zones than along its other source/drain zone and thus is asymmetrically doped. The channel zone of the other IGFET is doped more heavily close to both of its source/drain zones than at an intermediate location between them. More particularly, the channel zone of the second IGFET is typically symmetrically doped.
The multi-IGFET structure of the invention is particularly suitable for applications in which an IGFET, implemented with the symmetrically doped device, having source/drain zones that efficiently switch between functioning as source and functioning as drain needs to be combined with an IGFET, implemented with the asymmetrically doped device, having source/drain zones that permanently function respectively as source and drain. Although the symmetrical IGFET may have lower drive current than the asymmetrical IGFET, the ability to have the source/drain zones of one of the two IGFETs switch efficiently between functioning as source and functioning as drain compensates for reduced drive current.
In short, an IGFET having an asymmetrically doped channel zone is fabricated in a highly economical, highly efficient manner by employing the principles of the invention. No additional masking step(s) need be employed to asymmetrically dope the channel zone according to the invention. An IGFET having the so-doped channel zone performs very well with a high ratio of drive current to leakage current. The principles of the invention can readily be applied to combining an IGFET having a symmetrically doped channel zone with an IGFET having an asymmetrically doped channel zone. Accordingly, the invention provides a substantial advance over the prior art.